Several trends presently exist in the semiconductor and electronics industry. Devices are continually being made smaller, faster and requiring less power. One reason for these trends is that personal devices are being fabricated that are smaller and more portable, thereby relying on batteries as their primary supply. For example, cellular phones, personal computing devices, and personal sound systems are devices that are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are also requiring increased memory, more computational power and speed. In light of these trends, there is an ever increasing demand in the industry for smaller and faster transistors used to provide the core functionality of the integrated circuits used in these devices.
Accordingly, in the semiconductor industry there is a continuing trend toward manufacturing integrated circuits (ICs) with higher densities. To achieve higher densities, there has been and continues to be efforts toward scaling down dimensions (e.g., at submicron levels) on semiconductor wafers generally produced from bulk silicon. These trends are pushing the current technology to its limits. In order to accomplish these trends, high densities, smaller feature sizes, smaller separations between features, and more precise feature shapes are required in integrated circuits (ICs). This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges).
It can be appreciated that significant resources go into scaling down device dimensions and increasing packing densities. For example, significant man hours may be required to design such scaled down transistor devices, the equipment necessary to produce such devices may be expensive and/or processes related to producing such devices may have to be very tightly controlled and/or be operated under very specific conditions, etc. Accordingly, it can be appreciated that there is significant costs associated with exercising quality control over semiconductor fabrication, including, costs associated with discarding defective units, wasting raw materials and/or man hours, for example. Additionally, since the units are more tightly packed on the wafer, more units are lost when some or all of a wafer is defective and thus has to be discarded. The semiconductor industry is pursuing graphene to achieve some of the aforementioned goals with reduced defects. However, semiconductor devices utilizing graphene are currently difficult to construct.
Therefore, it would be advantageous to fabricate semiconductors utilizing graphene efficiently on existing wafers/workpieces that are currently utilized in transistor devices, for example, single crystal silicon wafers, SOI wafers, etc.